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GA20JT12-263 aug 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg1 of 11 s d g normally ? off silicon carbide junction transistor features package ? 175 c maximum operating temperature ? gate oxide free sic switch ? exceptional safe operating area ? excellent gain linearity ? temperature independent switching performance ? low output capacitance ? positive temperature coefficient of r ds,on ? suitable for connecting an anti-parallel diode ? to-263 ? advantages applications ? compatible with si mosfet/igbt gate drive ics ? > 20 s short-circuit withstand capability ? lowest-in-class conduction losses ? high circuit efficiency ? minimal input signal distortion ? high amplifier bandwidth ? ? hybrid electric vehicles (hev) ? solar inverters ? switched-mode power supply (smps) ? power factor correction (pfc) ? induction heating ? uninterruptible power supply (ups) ? motor drives table of contents section i: absolute maximum ratings ........................................................................................... ............... 1 ? section ii: static elect rical characteristics ................................................................................. .................. 2 ? section iii: dynamic elect rical charac teristics ............................................................................... ............. 2 ? section iv: figures ........................................................................................................... ............................... 3 ? section v: driving the ga20jt 12-263 ........................................................................................... ................ 7 ? section vi: packag e dimensions: ............................................................................................... ................. 11 ? section vii: spice model para meters ........................................................................................... .............. 12 ? section i: absolute maximum ratings parameter symbol conditions value unit notes drain ? source voltage v ds v gs = 0 v 1200 v continuous drain current i d t c = 25c 45 a fig. 17 continuous drain current i d t c = 145c 20 a fig. 17 continuous gate current i g 1.3 a turn-off safe operating area rbsoa t vj = 175 o c, clamped inductive load i d,max = 20 @ v ds v dsmax a fig. 19 short circuit safe operating area scsoa t vj = 175 o c, i g = 1 a, v ds = 800 v, non repetitive >20 s reverse gate ? source voltage v sg 30 v reverse drain ? source voltage v sd 25 v power dissipation p tot t c = 25 c / 145 c, t p > 100 ms 282 / 56 w fig. 16 storage temperature t stg -55 to 175 c s g d d v ds = 1200 v r ds(on) = 60 m i d (tc = 25c) = 45 a h fe (tc = 25c) = 80
GA20JT12-263 aug 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg2 of 11 section ii: static electrical characteristics a: on state b: off state c: thermal section iii: dynamic electrical characteristics a: capacitance and gate charge b: switching 1 1 ? all times are relative to the drain-source voltage v ds parameter symbol conditions value unit notes min. typical max. drain ? source on resistance r ds(on) i d = 20 a, t j = 25 c i d = 20 a, t j = 125 c i d = 20 a, t j = 175 c 60 96 128 m ? fig. 5 gate on voltage v gs,on i d = 20 a, v ds = 16 v, t j = 25 c i d = 20 a, v ds = 16 v, t j = 175 c 3.7 3.4 v fig. 4 dc current gain h fe v ds = 5 v, i d = 20 a, t j = 25 c v ds = 5 v, i d = 20 a, t j = 125 c v ds = 5 v, i d = 20 a, t j = 175 c 80 50 43 ? fig. 5 drain leakage current i dss v ds = 1200 v, v gs = 0 v, t j = 25 c v ds = 1200 v, v gs = 0 v, t j = 125 c v ds = 1200 v, v gs = 0 v, t j = 175 c 0.1 0.1 1 a fig. 6 gate leakage current i sg v sg = 20 v, t j = 25 c 20 na thermal resistance, junction - case r thjc 0.53 c/w fig. 20 parameter symbol conditions value unit notes min. typical max. input capacitance c iss v gs = 0 v, v ds = 800 v, f = 1 mhz 3091 pf fig. 9 reverse transfer/output capacitance c rss /c oss v ds = 800 v, f = 1 mhz 53 pf fig. 9 output capacitance stored energy e oss v gs = 0 v, v ds = 800 v, f = 1 mhz 17 j fig. 10 effective output capacitance, time related c oss,tr i d = constant, v gs = 0 v, v ds = 0?800 v 96 pf effective output capacitance, energy related c oss,er v gs = 0 v, v ds = 0?800 v 70 pf gate-source charge q gs v gs = -5?3 v 23 nc gate-drain charge q gd v gs = 0 v, v ds = 0?800 v 77 nc gate charge - total q g 100 nc internal gate resistance ? zero bias r g(int-zero) f = 1 mhz, v ac = 50 mv, v ds = 0 v, v gs = 0 v, t j = 175 oc 1.7 ? internal gate resistance ? on r g ( int-on ) v gs > 2.5 v, v ds = 0 v, t j = 175 oc 0.13 ? turn on delay time t d ( on ) t j = 25 oc, v ds = 800 v, i d = 20 a, resistive load refer to section v for additional driving information. 30 ns fall time, v ds t f 24 ns fig. 11, 13 turn off delay time t d ( off ) 21 ns rise time, v ds t r 17 ns fig. 12, 14 turn on delay time t d ( on ) t j = 175 oc, v ds = 800 v, i d = 20 a, resistive load 26 ns fall time, v ds t f 24 ns fig. 11 turn off delay time t d ( off ) 25 ns rise time, v ds t r 16 ns fig. 12 turn-on energy per pulse e on t j = 25 oc, v ds = 800 v, i d = 20 a, inductive load refer to section v. 505 j fig. 11, 13 turn-off energy per pulse e off 46 j fig. 12, 14 total switching energy e tot 551 j turn-on energy per pulse e on t j = 175 oc, v ds = 800 v, i d = 20 a, inductive load 514 j fig. 11 turn-off energy per pulse e off 41 j fig. 12 total switching energy e tot 555 j
GA20JT12-263 aug 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg3 of 11 section iv: figures a: static characteristic figures figure 1: typical output characteristics at 25 c figure 2: typical output characteristics at 125 c figure 3: typical output characteristics at 175 c figure 4: drain-source voltage vs. gate current figure 5: dc current gain and normalized on-resistance vs. temperature figure 6: dc current gain vs. drain current
GA20JT12-263 aug 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg4 of 11 figure 7: typical transfer characteristics figure 8: typical blocking characteristics b: dynamic characteristic figures figure 9: input, output, and reverse transfer capacitance figure 10: output capacitance stored energy figure 11: typical switching times and turn on energy losses vs. temperature figure 12: typical switching times and turn off energy losses vs. temperature
GA20JT12-263 aug 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg5 of 11 figure 13: typical switching times and turn on energy losses vs. drain current figure 14: typical switching times and turn off energy losses vs. drain current c: device derating figures figure 15: typical hard switched device power loss vs. switching frequency 2 figure 16: power derating curve figure 17: drain current derating vs. temperature figure 18: forward bias safe operating area at t c = 25 o c 2 ? representative values based on device conduction and switching loss. actual losses will depend on gate drive conditions, dev ice load, and circuit topology.
GA20JT12-263 aug 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg6 of 11 figure 19: turn-off safe operating area figure 20: transient thermal impedance figure 21: drain current derating vs. pulse width
GA20JT12-263 aug 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg7 of 11 section v: driving the GA20JT12-263 a: gate drive theory of operation the sjt transistor is a current controlled transistor which requires a positive gate curr ent for turn-on as well as to remain i n on-state. an ideal gate current waveform for ultra-fast switching of the sjt, while maintaining low gate drive losses, is shown in figure 22. figure 22: idealized gate current waveform a:1: gate currents, i g,pk /-i g,pk and voltages during turn-on and turn-off an sjt is rapidly switched from its blocking state to on-state, when the necessary gate charge, q g , for turn-on is supplied by a burst of high gate current, i g,on , until the gate-source capacitance, c gs , and gate-drain capacitance, c gd , are fully charged. , as an example, an i g,pon 3 a is required to achieve a 25 ns v ds fall time for a 800 v switching transition, due to the gate-drain charge, q gd of 77 nc for the GA20JT12-263. the i g,pon pulse should ideally terminate, when the drain volt age falls to its on-state value, in order to avoid unnecessary drive losses during the steady on-stat e. in practice, the rise time of the i g,on pulse is affected by the parasitic inductances, l par in the to-263 package and drive circuit. a voltage developed ac ross the parasitic inductance in the source path, l s , can de-bias the gate-source junction, when high drain currents begin to flow through the device. the applied gate voltage should be maintained high enough, above the v gs,on (see figure 7) level to counter these effects. a high negative peak current, -i g,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn-off. while sati sfactory turn off can be achieved with v gs = 0 v, a negative gate voltage v gs may be used in order to speed up the turn-off transition. a:2: steady on-state after the device is turned on, i g may be advantageously lowered to i g,steady for reducing unnecessary gate drive losses. the i g,steady is determined by noting the dc current gain, h fe , of the device from figures 5 and 6. the desired i g,steady is determined by the peak device junction temperature t j during operation, drain current i d , dc current gain h fe , and a 50 % safety margin to ensure operating the device in the satu ration region with low on-state voltage drop by the equation: , , 1.5
GA20JT12-263 aug 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg8 of 11 b: gate drive implementation examples b:1: using the ixys ix2204 gate driver the ixys ix2204 is a dual output gate drive integrated circuit which can be used to drive an sj t transistor by supplying the re quired gate drive current i g in a low-power gate drive solution. this conf iguration features an external gate capacitor, c g , which creates the brief current peak i g,on during device turn-on and i g,off during turn-off for fast switching and an external gate resistor r g(ext) to set the continuous gate current i g,steady required for the device to remain on. this configurati on is shown in figure 23 with further details provided below. figure 23: gate drive configuration using an ixys ix2204 gate drive ic. table 1: recommended component list for implementing the ix2204 based gate drive for the GA20JT12-263 reference component description suggested part r g ( ext ) gate resistance, external 2.2 ? , 2 w crm2512-jw-2r2elf c g gate capacitance 10 nf c1812c103j1gactu r cg damping resistor 1.0 ? , 0.5 w erj-1tyj1r0u d rg silicon schottky diode 40 v, 2 a ss24t3g r b bjt base resistor 1.0 ? , 0.5 w erj-1tyj1r0u q ha , q hb current boost npn 40 v, 8 a, silicon npn bjt mjd44h11 q l a , q lb current boost pnp 40 v, 8 a, silicon pnp bjt mjd45h11 u1 signal isolator opto-isolator ?or? transformer isolator a cpl-4800 / adum3210 x1 dc/dc converter, v gh supply v out = +20 v, v in = +12 v, 2 w, v iso = 5.2 kv mgj2d122005sc x2 dc/dc converter, v gl supply v out = +5 v, v in = +12 v, 3 w, v iso = 3.0 kv mev3s1205sc x3 dc/dc converter, v ee supply v out = -5 v, v in = +12 v, 2 w, v iso = 5.2 kv mgj2d122005sc b:2: voltage supply selection the ix2204 gate drive design requires three supply voltages v gh , v gl , and v ee (listed in table 2) optionally supplied through dc/dc converters. during device turn-on, v gh charges the external capacitor c g thereby delivering the narrow width, high current pulse i g,on to the sjt gate and charges the sjt?s inte rnal terminal capacitances c gd and c gs . for a given level of parasitic inductance in the gate circuit and sjt package, the rise time of i g,on is controlled by the choice of v gh and c g. during the steady on-state, v gl in combination with the internal and external gate resistances provi des a continuous gate current for the GA20JT12-263 to remain on. the v ee supply sets the gate negative during turn-off and steady off-state for faster switching and to av oid spurious turn-on which may be caused by external circuit noise. the power rating of the voltage supplies should be adequate to m eet the gate drive power requirements as determined by , 1 2 , 1 2 , ,
GA20JT12-263 aug 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg9 of 11 table 2: ix2204 gate drive example component list symbol parameter values range typical v gh supply voltage, driver output a 15 ? 20 + 20.0 v gl supply voltage, driver output b 5.0 ? 7.0 + 5.0 v ee negative supply voltage -10 ? gnd - 5.0 b:3: gate capacitor c g selection figure 24: primary gate drive circuit passive components with series gate resistance schottky rectifier. an external gate capacitor c g connected directly to the device gate pin delivers the positive current peak i g,on during device turn-on and the negative current peak i g,off during turn-off. a low value resistor r cg is connected in series with c g to damp potential high-frequency oscillation. a high value resistor r ch in parallel with c g sets the sjt gate to a defined potential (-v ee ) during steady off-state. at device turn-on, c g is pulled to v gh which produces a transient peak of gate voltage and current. this current peak rapidly charges the internal sjt c gs and c gd capacitances. a schottky diode, d rg , in series with r g(ext) blocks any c g induced current from draining out through r g(ext) and ensures that all of the charge within c g flows only into the device gate, allowing for an ultra-fast device turn-on. during steady on- state, a potential of v gh - v gs = v gh ? 3 v is across c g . when the device is turned off, c g is pulled to negative v ee and v gs is pulled to a transient peak of v gs,turn-off = v ee ? (v gh ? 3 v), this induces the negative current peak i g,off out of the gate which discharges the sjt internal capacitances. b:4: external gate resistor r g(ext) selection an external gate resistor r g(ext) connected directly to the sjt gate pin acts to deliver a continuous current i g,steady during steady on-state. the gate current is determined by: , the on-state gate-source voltage v gs(fwd) can be approximated to 3 v and the schottky on-state voltage v sch can be approximated to 0.3 v which simplifies the equation to: , 3.3 the desired i g,steady is determined by the peak device junction temperature t j during operation, drain current i d , dc current gain , and a 50 % safety margin to avoid operating the device in saturation. i g,steady may also be approximated from the temperature dependent on-state curves of the device in figures 1 ? 3, provi ded that a 50 % increase is given. table 3: passive output component list symbol parameter values range typical units c g gate capacitor, external 5 ? 20 10 nf r cg damping resistor of gate capacitor 0.5 ? 2.0 1.0 ? r ch charging resistor 500 ? 10k 1k ? r g ( ext ) gate resistor, external 0.5 ? 10 2.0 ? r g ( int-on ) gate resistance, internal, on-state 0.05 ? 0.2 0.13 ? d rg schottky diode of gate resistor -- -- i g c g r g(ext) d s d rg r g(int) r cg v gl / v ee v gh / v ee r ch g
GA20JT12-263 aug 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg10 of 11 b:5: optional gate current boost network an optional output totem-pole network may be attached to the ix2204 output pins as shown in figur e 23 using either silicon bjts (shown) or mosfets. this configuration allows the ix2204 to directly driv e the bjt bases or mosfet gates and not supply the full peak and steady state gate current entering the sjt gate. the primary gate curr ent delivery device is transferr ed to the discrete components wh ich have higher power dissipation ratings than the ix2204. b:6: voltage supply isolation the dc/dc supply voltage converters are suggested to prov ide isolation at a minimu m of twice the working v ds on the sjt transistor during off-state to provide adequate protection to circuitry external to the gate drive ci rcuit. suggested dc/dc converters have an is olation of 3.0 kv or greater. alternatively, dc/dc conver ter galvanic isolation may be bypassed and direct connection of variable voltage supplie s may be done, this may be convenient during testing and prototyping but carries risk and is not s uggested for extended usage. figure 25: typical dc/dc converter configuration b:7: signal isolation the gate supply signal is suggested to be isolated to twice the working v ds on the sjt during off-state to provide adequate protection to circuitry external to the gate driv e circuit. this may be done using opto or galvanic isolation techniques. b:8: additional features the ix2204 has additional functionality avail able which is unused in the given config uration. desaturation detection and fault status monitoring may be implemented by un-grounding the desat, blank, and trista te pins and configuring them as recommended in the ix2204 datasheet, available from ixys. active mill er clamping is also available on other gat e drive ics which may also be desired in s ome sjt switching applications but is not required, refer to s pecific gate drive ic datasheets for more information. c: alternative gate drive ics the sjt transistor may be driven similarly to silicon igbts or mosfets in which a gate driver ic is used to supply positive gat e current peaks to the device at turn-on and negative current peaks at turn-o ff. table 4 features a partial list of alternative gate drive ics which may be used; specific product information should be obtained from the indi vidual product manufacturers. table 4: additional commercial gate drivers compatible with GA20JT12-263 features manufacturer part number optical signal isolation desaturation detection active miller gate clamping 3 high side capability number of outputs a vago tech. hcpl-316j ? ? ? ? 1 a vago tech. hcpl-322j ? ? ? ? 1 ixys ixd_604 ? ? ? ? 2 ixys ixd_614 ? ? ? ? 1 micrel mic4452yn ? ? ? ? 1 microsemi lx4510 ? ? ? ? 1 texas instruments ucc27322 ? ? ? ? 1 3 ? active miller gate clamping recommended for v ee = gnd switching applications as sjt and/or output bjt secondary gate discharge path.
GA20JT12-263 aug 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg11 of 11 section vi: package dimensions: to-263 package outline note 1. controlled dimension is inch. di mension in bracket is millimeter. 2. dimensions do not include end fl ash, mold flash, material protrusions revision history date revision comments supersedes 2014/08/25 0 initial release published by genesic semiconductor, inc. 43670 trade center place suite 155 dulles, va 20166 genesic semiconductor, inc. reserves right to make changes to the product specificat ions and data in this document without noti ce. genesic disclaims all and any warranty and liability arising out of use or application of any product. no license, express or i mplied to any intellectual property rights is granted by this document. unless otherwise expressly indicated, genesic products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic cont rol and weapons systems, nor in applications where their failure may result in death , personal injury and/or property damage.
GA20JT12-263 aug 2014 http://www.genesicsemi.com/commerc ial-sic/sic-junction-transistors/ pg 1 of 1 section vii: spice model parameters this is a secure document. please copy this code from the spice model pdf file on our website (http://www.genesicsemi.com/images/products_sic /sjt/GA20JT12-263_spice.pdf) into ltspice (version 4) software for simulation of the GA20JT12-263. * model of genesic semiconductor inc. * * $revision: 2.0 $ * $date: 25-aug-2014 $ * * genesic semiconductor inc. * 43670 trade center place ste. 155 * dulles, va 20166 * * copyright (c) 2014 genesic semiconductor inc. * all rights reserved * * these models are provided "as is, where is, and with no warranty * of any kind either expressed or implied, including but not limited * to any implied warranties of merchantability and fitness for a * particular purpose." * models accurate up to 2 times rated drain current. * .model ga20jt12 npn + is 5.00e-47 + ise 1.26e-28 + eg 3.23 + bf 78 + br 0.55 + ikf 5000 + nf 1 + ne 2 + rb 3.09 + irb 0.006 + rbm 0.101 + re 0.005 + rc 0.050 + cjc 752.4e-12 + vjc 3.17 + mjc 0.480 + cje 3.014e-09 + vje 3.568 + mje 0.538 + xti 3 + xtb -1.5 + trc1 8.500e-3 + vceo 1200 + icrating 20 + mfg genesic_semiconductor * * end of ga20jt12 spice model

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